As is known in the art, an important requirement for “transistor” amplifier design is establishment of a stable DC operation condition of the associated transistors. MESFET and HEMT amplifiers are biased at a quiescent drain current to achieve desired performance. Setting this quiescent drain current (Idq) is usually accomplished by adjusting the DC voltage supplied to the gate of the transistor. Although in principle the gate voltage (Vg) can be determined readily from the drain current (Id) versus Vg transfer characteristic of a typical device, inherent sensitivities of the FET characteristics to fabrication process and temperature preclude using of a fixed Vg.
As is also know, a circuit for adjusting Vg preferably on a per amplifier basis should ensure that the quiescent drain current (Idq) is set near the nominal target value. Typical implementations include: supplying externally an individual Vg voltage to each amplifier; adding a resistor ladder network on chip to generate several candidate Vg voltages from a fixed supply voltage; screening and dividing parts into several Vg bins. All known options require some level of testing to determine first how each part or a group of parts has to be biased. Then assembly is tailored to that particular part or group of parts. These steps add significant time and cost to the product.
One technique suggested is described in U.S. Pat. No. 5,793,194, inventor Lewis issued Aug. 11, 1998 and assigned to the same assignee as the present invention. Such U.S. patent describes voltage bias and temperature compensation circuits. While such circuits operate effectively in many applications, they operate with a resistor in the source to ground path to supply the requisite gate voltage. This technique may be inadequate for some power amplifier applications since the resistor adversely affects the power added efficiency of the amplifier.
Other bias circuits are described in U.S. Pat. Nos. 5,724,004, 5,793,194, 5,889,426, 6,114,901, 6,304,130 and in an article entitled “A 1.9 GHz Fully Integrated PHS Power Amplifier With a Novel Automatic Gate-Bias Control Circuit”, by Singh et al., published 1998 in the IEEE MTT-S Digest 0-7803-4471 5/98.